Memory persistency models sculpt the destiny of Non-Volatile Memory (NVM) writes. While meticulously outlined for Intel-x86 and Arm architectures, these models lack empirical validation on real-world machines. Traditional validation methods for memory consistency models prove inadequate, as test programs struggle to distinguish volatile cache reads from reads in NVM. Physical bus probing also encounters limitations, given the persistence domain’s extension into an unprobed buffer within the memory controller.

To tackle the intricate challenge of navigating the memory hierarchy, particularly within Intel architectures, we propose a methodical memory hierarchy timing attack. By time-stamping instructions, we capture temporal nuances and conduct a detailed analysis to infer the access destination within the memory hierarchy. This strategic attack exploits inherent timing variations, extracting insightful inferences about the exact location of the stored value.

Yet, understanding the complexities of the memory hierarchy is no trivial task. Interpretations of the timing information depend heavily on the intricacies of the architecture and the specific characteristics of the application.

In addressing this complexity, we leverage model learning techniques to craft a machine-readable representation of the target system. Cultivated through observations in a black-box fashion, this model enables us to automatically discern timing and ordering patterns of memory instructions.